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This research addresses the challenges faced by chip designers in the era of multi-processor architectures. It proposes new statistical models to ensure reliable performance in Network-on-Chip designs, focusing on traffic patterns and Quality-of-Service guarantees.
As chip multi-processor architectures are replacing single-processor architectures and reshaping the semiconductor industry, chip designers can hardly use their old models and benchmarks anymore.
While designers were used to deterministic and reliable performance in the chips, they now face networks with unreliable traffic patterns, unreliable throughput and unreliable delays, hence making it hard to provide any guaranteed Quality-of-Service (QoS).
In this proposal, we argue that chip designers…
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