CORDIS Project
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This project investigates formal verification methods to ensure the correctness of hardware and software designs. By enhancing existing verification techniques with quality measures, the research aims to improve the reliability of automatically generated systems.
Formal verification is the study of algorithms and tools for the development of correct hardware and software designs.
Two fundamental problems in formal verification are temporal logic model checking -- given a mathematical model of the system and a temporal-logic formula that specifies the desired behavior of the system, decide whether the model satisfies the formula, and synthesis -- given a temporal-logic formula that specifies the desired behavior, generate a system that satisfies the speci…
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